1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to an alternate metal virtual ground (AMG) EPROM array that is based on an asymmetrical cell architecture.
2. Discussion of the Prior Art
U.S. patent application Ser. No. 539,657, filed by Boaz Eitan on Jun. 13, 1990 for EPROM VIRTUAL GROUND ARRAY, discloses an AMG EPROM cell array and its associated process flow. The Eitan AMG array is attractive because it allows high density EPROMs to be fabricated without using aggressive fabrication techniques and design rules.
The basic idea of the Eitan array is the use of a "cross-point" EPROM cell, i.e. a cell which is defined by the perpendicular crossing of a polysilicon (poly 1) floating gate and a polysilicon (poly 2) word line in a virtual ground array. In order to avoid drain turn-on, i.e. electron leakage from unselected cells on the same bit line as the selected cell, metal contacts silicon only on alternate bit lines and the non-contacted source bit lines are connected to ground potential only via access select transistors, as shown in the FIG. 1 layout.
Additionally, in the Eitan array, each drain bit line is contacted only once every 64 cells, each group of 64 cells on the same drain bit line constituting one segment. Typically, 16 segments are combined to define a block of cells in the array in that is 16 bits wide. Thus, when programming a particular cell, only one 64-cell segment need be addressed. All other segments are "off". Therefore, the cells in these unselected segments are not susceptible to leakage.
By strapping alternate bit lines and by utilizing select transistors, the Eitan array transfers the scaling limitation of the array from the metal pitch to the polysilicon pitch. As a result, an EPROM cell size of 2.56 .mu.m.sup.2 with 0.8 .mu.m layout rules can be realized for 4 Mbit memory applications and beyond. Furthermore, by introducing select transistors, drain turn-on induced punch through can be minimized and the effective channel length of the cell can be reduced to as low as 0.25 .mu.m, thereby increasing cell read current and enhancing programmability.
However, due to the symmetry of the stacked gate cell utilized in the Eitan AMG array, a neighboring unselected cell can be unintentionally written during a write operation. Furthermore, soft write of the selected cell during read operations limits bit line bias and memory performance.
More specifically, as shown in FIGS. 2A and 2B, to read cell B in the conventional AMG array, word line WL(i+63) and select lines Sel are biased at 5 V while select lines Sel are grounded; bit line m-1 is grounded, while the other bit lines are biased at a bit line voltage V.sub.BL with the sense amplifier (not shown) attached to bit line m. With this bias scheme, the potential soft write of cell B limits the bit line bias voltage V.sub.BL and, thus, cell current and memory performance.
FIG. 3 shows the soft write characteristics of the conventional AMG EPROM cell with a W/L of 0.8.mu./0.8.mu.. According to the FIG. 3 data, in order no guarantee 10 year data retention, the bit line voltage V.sub.BL must be less than 1.47 V. Due to the low coupling ratio (0.4.about.0.45) and the low bit line voltage V.sub.BL, single cell read current (Vg=5 V and Vd=1.2 V) is less than 60 .mu.A. For a multi-Mbit EPROM array, low cell read current combined with high bit line capacitance results in slow memory access.
As stated above, in addition to low cell current, unintentional write of a neighboring unselected cell during a write operation poses a data retention problem for the conventional AMG array.
Referring again to FIGS. 2A and 2B, to write cell B, word line WL(i+63) and select lines Sel are biased at 12 V while select lines Sel are grounded. Bit lines m and m-1 are biased at 7 V and 0 V, respectively, while unselected bit lines are left to float. With this bias scheme, cell D can be unintentionally written because of the high bit line bias at the drain and high bit line capacitance attached to the source.
With 0.80 .mu.m layout rules, a conservative estimate gives a bit line capacitance of 5.7 pF for a 16 Mbit array. When the conventional AMG EPROM array is laid out in blocks of 16 bits wide, the worst case total bit line capacitance attached to the source of cell D can be as high as 40 pF since a 12 V word line bias effectively shorts 7 bit lines to the source of cell D.
FIGS. 4A and 4B show the unintentional write characteristics of the conventional AMG cell with various capacitors attached to the source. As shown in FIG. 4A, when a 38 pF capacitor is attached to the source, unintentional write can cause an erased cell threshold voltage V.sub.th to increase from 1.6 V to nearly 4 V, while, as shown in FIG. 4B, cell current drops from 60 .mu.A to less than 15 .mu.A. Thus, data loss can occur.
The unintentional write problem discussed above can be minimized by reducing the bias on the select lines Sel of the array to increase the voltage drop across the select transistor. However, under these bias conditions, the bit line charging current is now distributed between two select transistors and cell C, which can now be unintentionally written. Furthermore, a low bias voltage on select lines Sel results in a high source potential for the selected cell (cell B in FIG. 2) because both the write current of the selected cell and the punch-through current of the 63 unselected cells must be supplied through two select transistors. The high source potential results in a low voltage drop across the channel and a high cell threshold voltage (body effect) which can significantly degrade cell programmability.
To insure that cells with the highest series resistance, i.e. cells along word lines WL(i+31) and WL(i+32), and under the worst-case processing conditions, can be properly written within 10 .mu.sec., a bit line bias greater than 7 V is needed. Unfortunately, high bit line bias exacerbates both the unintentional write problem for cell C and the punch-through problem for the 63 unselected cells.
Thus, without significant modification, the operating margin of a 16 Mbit EPROM array based on the conventional AMG architecture is limited.
Yoshikawa et al, "An Asymmetrical Lightly Doped Source (ALDS) Cell for Virtual Ground High Density EPROMs", IEDM, p. 432, 1988, disclose an EPROM cell structure that utilizes a lightly doped source region. As shown in FIG. 5A, an N.sup.- implant and an N.sup.+ pull-back implant at the source creates an asymmetrical cell that is suitable for use in a high density virtual ground EPROM array because the problem of unintentional write during a write operation is eliminated. FIG. 5B shows a drawing convention that will be used in the discussion below wherein a black dot is used to depict the N.sup.- source and the asymmetrical nature of the call.